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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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#include <pl011.h>
Data Fields | |
| volatile unsigned int | dr |
| volatile unsigned int | rsrecr |
| volatile unsigned int | dont_use_a |
| volatile unsigned int | dont_use_b |
| volatile unsigned int | dont_use_c |
| volatile unsigned int | dont_use_d |
| volatile unsigned int | fr |
| volatile unsigned int | dont_use_e |
| volatile unsigned int | ilpr |
| volatile unsigned int | ibrd |
| volatile unsigned int | fbrd |
| volatile unsigned int | lcrh |
| volatile unsigned int | cr |
| volatile unsigned int | ifls |
| volatile unsigned int | imsc |
| volatile unsigned int | ris |
| volatile unsigned int | mis |
| volatile unsigned int | icr |
Control and status registers for the PL011 UART. This structure is mapped directly to the base address for the CSR.
| volatile unsigned int pl011_uart_csreg::cr |
Control Register
| volatile unsigned int pl011_uart_csreg::dont_use_b |
spacer
| volatile unsigned int pl011_uart_csreg::dont_use_c |
spacer
| volatile unsigned int pl011_uart_csreg::dont_use_d |
spacer
| volatile unsigned int pl011_uart_csreg::dr |
Data Register
| volatile unsigned int pl011_uart_csreg::fbrd |
Fractional baud rate divisor
| volatile unsigned int pl011_uart_csreg::fr |
spacer Flag Register
| volatile unsigned int pl011_uart_csreg::ibrd |
Integer baud rate divisor
| volatile unsigned int pl011_uart_csreg::icr |
Interupt Clear Register
| volatile unsigned int pl011_uart_csreg::ifls |
Interupt FIFO level select register
| volatile unsigned int pl011_uart_csreg::ilpr |
spacer Not in use
| volatile unsigned int pl011_uart_csreg::imsc |
Interupt Mask Set Clear Register
| volatile unsigned int pl011_uart_csreg::lcrh |
Line Control Register
| volatile unsigned int pl011_uart_csreg::mis |
Masked Interupt Status Register
| volatile unsigned int pl011_uart_csreg::ris |
Raw Interupt Status Register
| volatile unsigned int pl011_uart_csreg::rsrecr |
Receive status/error clear register
1.8.5