Embedded Xinu Operating System
An ongoing research project and educational operating system.
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Data Structures | |
struct | pl011_uart_csreg |
Macros | |
#define | PL011_DR_OE (1<<11) |
#define | PL011_DR_BE (1<<10) |
#define | PL011_DR_PE (1<<9) |
#define | PL011_DR_FE (1<<8) |
#define | PL011_RSRECR_OE (1<<3) |
#define | PL011_RSRECR_BE (1<<2) |
#define | PL011_RSRECR_PE (1<<1) |
#define | PL011_RSRECR_FE (1<<0) |
#define | PL011_FR_RI (1<<8) |
#define | PL011_FR_TXFE (1<<7) |
#define | PL011_FR_RXFF (1<<6) |
#define | PL011_FR_TXFF (1<<5) |
#define | PL011_FR_RXFE (1<<4) |
#define | PL011_FR_BUSY (1<<3) |
#define | PL011_FR_DCD (1<<2) |
#define | PL011_FR_DSR (1<<1) |
#define | PL011_FR_CTS (1<<0) |
#define | PL011_LCRH_SPS (1<<7) |
#define | PL011_LCRH_WLEN_8BIT (0b11<<5) |
#define | PL011_LCRH_WLEN_7BIT (0b10<<5) |
#define | PL011_LCRH_WLEN_6BIT (0b01<<5) |
#define | PL011_LCRH_WLEN_5BIT (0b00<<5) |
#define | PL011_LCRH_FEN (1<<4) |
#define | PL011_LCRH_STP2 (1<<3) |
#define | PL011_LCRH_EPS (1<<2) |
#define | PL011_LCRH_PEN (1<<1) |
#define | PL011_LCRH_BRK (1<<0) |
#define | PL011_CR_CTSEN (1<<15) |
#define | PL011_CR_RTSEN (1<<14) |
#define | PL011_CR_OUT2 (1<<13) |
#define | PL011_CR_OUT1 (1<<12) |
#define | PL011_CR_RTS (1<<11) |
#define | PL011_CR_DTR (1<<10) |
#define | PL011_CR_RXE (1<<9) |
#define | PL011_CR_TXE (1<<8) |
#define | PL011_CR_LBE (1<<7) |
#define | PL011_CR_SIRLP (1<<2) |
#define | PL011_CR_SIREN (1<<1) |
#define | PL011_CR_UARTEN (1<<0) |
#define | PL011_IFLS_RXIFLSEL_EIGHTH (0b000<<3) |
#define | PL011_IFLS_RXIFLSEL_QUARTER (0b001<<3) |
#define | PL011_IFLS_RXIFLSEL_HALF (0b010<<3) |
#define | PL011_IFLS_RXIFLSEL_THREEQUARTERS (0b011<<3) |
#define | PL011_IFLS_RXIFLSEL_SEVENEIGHTHS (0b100<<3) |
#define | PL011_IFLS_TXIFLSEL_EIGHTH (0b000<<0) |
#define | PL011_IFLS_TXIFLSEL_QUARTER (0b001<<0) |
#define | PL011_IFLS_TXIFLSEL_HALF (0b010<<0) |
#define | PL011_IFLS_TXIFLSEL_THREEQUARTERS (0b011<<0) |
#define | PL011_IFLS_TXIFLSEL_SEVENEIGHTHS (0b100<<0) |
#define | PL011_IMSC_OEIM (1<<10) |
#define | PL011_IMSC_BEIN (1<<9) |
#define | PL011_IMSC_PEIM (1<<8) |
#define | PL011_IMSC_FEIM (1<<7) |
#define | PL011_IMSC_RTIM (1<<6) |
#define | PL011_IMSC_TXIM (1<<5) |
#define | PL011_IMSC_RXIM (1<<4) |
#define | PL011_IMSC_DSRMIM (1<<3) |
#define | PL011_IMSC_DCDMIM (1<<2) |
#define | PL011_IMSC_CTSMIM (1<<1) |
#define | PL011_IMSC_RIMIM (1<<0) |
#define | PL011_RIS_OERIS (1<<10) |
#define | PL011_RIS_BERIS (1<<9) |
#define | PL011_RIS_PERIS (1<<8) |
#define | PL011_RIS_FERIS (1<<7) |
#define | PL011_RIS_RTRIS (1<<6) |
#define | PL011_RIS_TXRIS (1<<5) |
#define | PL011_RIS_RXRIS (1<<4) |
#define | PL011_RIS_DSRRMIS (1<<3) |
#define | PL011_RIS_DCDRMIS (1<<2) |
#define | PL011_RIS_CTSRMIS (1<<1) |
#define | PL011_RIS_RIRMIS (1<<0) |
#define | PL011_MIS_OEMIS (1<<10) |
#define | PL011_MIS_BEMIS (1<<9) |
#define | PL011_MIS_PEMIS (1<<8) |
#define | PL011_MIS_FEMIS (1<<7) |
#define | PL011_MIS_RTMIS (1<<6) |
#define | PL011_MIS_TXMIS (1<<5) |
#define | PL011_MIS_RXMIS (1<<4) |
#define | PL011_MIS_DSRMMIS (1<<3) |
#define | PL011_MIS_DCDMMIS (1<<2) |
#define | PL011_MIS_CTSMMIS (1<<1) |
#define | PL011_MIS_RIMMIS (1<<0) |
#define | PL011_ICR_OEIC (1<<10) |
#define | PL011_ICR_BEIC (1<<9) |
#define | PL011_ICR_PEIC (1<<8) |
#define | PL011_ICR_FEIC (1<<7) |
#define | PL011_ICR_RTIC (1<<6) |
#define | PL011_ICR_TXIC (1<<5) |
#define | PL011_ICR_RXIC (1<<4) |
#define | PL011_ICR_DSRMIC (1<<3) |
#define | PL011_ICR_DCDMIC (1<<2) |
#define | PL011_ICR_CTSMIC (1<<1) |
#define | PL011_ICR_RIMIC (1<<0) |
#define | PL011_FIFO_LEN 8 |
#define | PL011_BAUD_INT(x) (UARTCLK / (16 * (x))) |
#define | PL011_BAUD_FRAC(x) (int)((((UARTCLK / (16.0 * (x)))-PL011_BAUD_INT(x))*64.0)+0.5) |
#define PL011_FIFO_LEN 8 |
During testing on a Raspberry Pi, I could only sen 8.