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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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#include <usb_dwc_regs.h>
Data Fields | |
| uint32_t | val |
| struct { | |
| uint32_t stuff: 3 | |
| uint32_t sof_intr: 1 | |
| uint32_t morestuff: 20 | |
| uint32_t port_intr: 1 | |
| uint32_t host_channel_intr: 1 | |
| uint32_t evenmorestuff: 6 | |
| }; | |
0x014 : Core Interrupt Register.
This register contains the state of pending top-level DWC interrupts. 1 means interrupt pending while 0 means no interrupt pending.
Note that at least for port_intr and host_channel_intr, software must clear the interrupt somewhere else rather than by writing to this register.
| uint32_t dwc_regs::dwc_core_interrupts::host_channel_intr |
Channel interrupt occurred. Software must examine the Host All Channels Interrupt Register to determine which channel(s) have pending interrupts, then handle and clear the interrupts for these channels.
| uint32_t dwc_regs::dwc_core_interrupts::port_intr |
Host port status changed. Software must examine the Host Port Control and Status Register to determine the current status of the host port and clear any flags in it that indicate a status change.
| uint32_t dwc_regs::dwc_core_interrupts::sof_intr |
Start of Frame. TODO
1.8.5
