usb_dwc_regs.h

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/* Embedded Xinu, Copyright (C) 2013.  All rights reserved. */

#ifndef _USB_DWC_REGS_H_
#define _USB_DWC_REGS_H_

#include <usb_util.h>

#define DWC_NUM_CHANNELS 8

struct dwc_regs {

    /* 0x000 : OTG Control */
    uint32_t otg_control;

    /* 0x004 : OTG Interrupt */
    uint32_t otg_interrupt;

    uint32_t ahb_configuration;

#define DWC_AHB_INTERRUPT_ENABLE  (1 << 0)

#define BCM_DWC_AHB_AXI_WAIT      (1 << 4)

#define DWC_AHB_DMA_ENABLE        (1 << 5)

    /* 0x01c : Core USB configuration */
    uint32_t core_usb_configuration;


    uint32_t core_reset;

#define DWC_AHB_MASTER_IDLE (1 << 31)

#define DWC_SOFT_RESET      (1 << 0)

    union dwc_core_interrupts {
        uint32_t val;
        struct {
            uint32_t stuff             : 3;

            uint32_t sof_intr          : 1;

            uint32_t morestuff         : 20;

            uint32_t port_intr         : 1;     /* Bit 24 */

            uint32_t host_channel_intr : 1;     /* Bit 25 */

            uint32_t evenmorestuff     : 6;
        };
    } core_interrupts;

    union dwc_core_interrupts core_interrupt_mask;

    /* 0x01c : Receive Status Queue Read */
    uint32_t receive_status;

    /* 0x020 : Receive Status Queue Read & Pop */
    uint32_t receive_status_pop;

    uint32_t rx_fifo_size;

    uint32_t nonperiodic_tx_fifo_size;

    /* 0x02c : Non Periodic Transmit FIFO/Queue Status Register */
    uint32_t nonperiodic_tx_fifo_status;

    /* 0x030 */
    uint32_t i2c_control;

    /* 0x034 */
    uint32_t phy_vendor_control;

    /* 0x038 */
    uint32_t gpio;

    /* 0x03c */
    uint32_t user_id;

    /* 0x040 */
    uint32_t vendor_id;

    /* 0x044 */
    uint32_t hwcfg1;

    /* 0x048 */
    uint32_t hwcfg2;

    uint32_t hwcfg3;

    /* 0x050 */
    uint32_t hwcfg4;

    /* 0x054 */
    uint32_t core_lpm_configuration;

    /* 0x058 */
    uint32_t global_powerDn;

    /* 0x05c */
    uint32_t global_fifo_config;

    /* 0x060 */
    uint32_t adp_control;

    /* 0x064 */
    uint32_t reserved_0x64[39];

    uint32_t host_periodic_tx_fifo_size;

    /* TODO */
    uint32_t stuff[191];

    /* 0x400 */
    uint32_t host_configuration;

    /* 0x404 */
    uint32_t host_frame_interval;

    /* 0x408 */
    uint32_t host_frame_number;

    /* 0x40c */
    uint32_t host_reserved_0x40c;

    /* 0x410 */
    uint32_t host_fifo_status;

    uint32_t host_channels_interrupt;

    uint32_t host_channels_interrupt_mask;

    /* 0x41c */
    uint32_t host_frame_list;

    /* 0x420 */
    uint32_t host_reserved_0x420[8];

    union dwc_host_port_ctrlstatus {
        uint32_t val;
        struct {
            uint32_t connected : 1; /* Bit 0 */

            uint32_t connected_changed : 1; /* Bit 1 */

            uint32_t enabled : 1; /* Bit 2 */

            uint32_t enabled_changed : 1; /* Bit 3 */

            uint32_t overcurrent : 1; /* Bit 4 */

            uint32_t overcurrent_changed : 1; /* Bit 5 */

            uint32_t resume : 1; /* Bit 6 */

            uint32_t suspended : 1; /* Bit 7 */

            uint32_t reset : 1; /* Bit 8 */

            uint32_t reserved : 1; /* Bit 9 */

            uint32_t line_status : 2; /* Bits 10-11*/

            uint32_t powered : 1; /* Bit 12 */

            uint32_t test_control : 4; /* Bits 13-16 */

            uint32_t speed : 2; /* Bits 17-18 */

            uint32_t reserved2 : 13; /* Bits 19-32 */

        };
    } host_port_ctrlstatus;

    uint32_t host_reserved_0x444[47];

    struct dwc_host_channel {

        union dwc_host_channel_characteristics {
            uint32_t val;
            struct {
                uint32_t max_packet_size     : 11; /* Bits 0-10  */

                uint32_t endpoint_number     : 4;  /* Bits 11-14 */

                uint32_t endpoint_direction  : 1;  /* Bit  15    */

                uint32_t reserved            : 1;  /* Bit  16    */

                uint32_t low_speed           : 1;  /* Bit  17    */

                uint32_t endpoint_type       : 2;  /* Bits 18-19 */

                uint32_t packets_per_frame   : 2;  /* Bits 20-21 */

                uint32_t device_address      : 7;  /* Bits 22-28 */

                uint32_t odd_frame           : 1;  /* Bit  29    */

                uint32_t channel_disable     : 1;  /* Bit  30    */

                uint32_t channel_enable      : 1;  /* Bit  31    */
            };
        } characteristics;

        union dwc_host_channel_split_control {
            uint32_t val;
            struct {
                uint32_t port_address          : 7;  /* Bits 0-6   */

                uint32_t hub_address           : 7;  /* Bits 7-13  */

                uint32_t transaction_position  : 2;  /* Bits 14-15 */

                uint32_t complete_split        : 1;  /* Bit  16    */

                uint32_t reserved              : 14; /* Bits 17-30 */

                uint32_t split_enable          : 1;  /* Bit  31    */
            };
        } split_control;

        union dwc_host_channel_interrupts {
            uint32_t val;
            struct {
                uint32_t transfer_completed       : 1;  /* Bit 0     */

                uint32_t channel_halted           : 1;  /* Bit 1     */

                uint32_t ahb_error                : 1;  /* Bit 2     */

                uint32_t stall_response_received  : 1;  /* Bit 3     */

                uint32_t nak_response_received    : 1;  /* Bit 4     */

                uint32_t ack_response_received    : 1;  /* Bit 5     */

                uint32_t nyet_response_received   : 1;  /* Bit 6     */

                uint32_t transaction_error        : 1;  /* Bit 7     */

                uint32_t babble_error             : 1;  /* Bit 8     */

                uint32_t frame_overrun            : 1;  /* Bit 9     */

                uint32_t data_toggle_error        : 1;  /* Bit 10    */

                uint32_t buffer_not_available     : 1;  /* Bit 11    */
                uint32_t excess_transaction_error : 1;  /* Bit 12    */
                uint32_t frame_list_rollover      : 1;  /* Bit 13    */
                uint32_t reserved                 : 18; /* Bits 14-31 */
            };
        } interrupts;

        union dwc_host_channel_interrupts interrupt_mask;

        union dwc_host_channel_transfer {
            uint32_t val;
            struct {
                uint32_t size         : 19; /* Bits 0-18  */

                uint32_t packet_count : 10; /* Bits 19-28 */

                uint32_t packet_id    : 2;  /* Bits 29-30 */

                uint32_t do_ping      : 1;  /* Bit  31    */
            };
        } transfer;

        uint32_t dma_address;

        uint32_t reserved_1;
        uint32_t reserved_2;
    } host_channels[DWC_NUM_CHANNELS];

    uint32_t host_reserved_after_channels[(0x800 - 0x500 -
                        (DWC_NUM_CHANNELS * sizeof(struct dwc_host_channel))) /
                         sizeof(uint32_t)];

    /* 0x800 */

    uint32_t reserved_0x800[(0xe00 - 0x800) / sizeof(uint32_t)];

    /* 0xe00 : Power and Clock Gating Control Register */
    uint32_t power;
};

/* Make sure the registers are declared correctly.  This is dummy code that will
 * be compiled into nothing.  */
static inline void _dwc_check_regs(void)
{
    STATIC_ASSERT(offsetof(struct dwc_regs, vendor_id) == 0x40);
    STATIC_ASSERT(offsetof(struct dwc_regs, host_periodic_tx_fifo_size) == 0x100);
    STATIC_ASSERT(offsetof(struct dwc_regs, host_configuration) == 0x400);
    STATIC_ASSERT(offsetof(struct dwc_regs, host_port_ctrlstatus) == 0x440);
    STATIC_ASSERT(offsetof(struct dwc_regs, reserved_0x800) == 0x800);
    STATIC_ASSERT(offsetof(struct dwc_regs, power) == 0xe00);
}

#endif /* _USB_DWC_REGS_H_ */