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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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#include <usb_dwc_regs.h>
Data Structures | |
| union | dwc_core_interrupts |
| struct | dwc_host_channel |
| union | dwc_host_port_ctrlstatus |
Data Fields | |
| uint32_t | otg_control |
| uint32_t | otg_interrupt |
| uint32_t | ahb_configuration |
| uint32_t | core_usb_configuration |
| uint32_t | core_reset |
| union dwc_regs::dwc_core_interrupts | core_interrupts |
| union dwc_core_interrupts | core_interrupt_mask |
| uint32_t | receive_status |
| uint32_t | receive_status_pop |
| uint32_t | rx_fifo_size |
| uint32_t | nonperiodic_tx_fifo_size |
| uint32_t | nonperiodic_tx_fifo_status |
| uint32_t | i2c_control |
| uint32_t | phy_vendor_control |
| uint32_t | gpio |
| uint32_t | user_id |
| uint32_t | vendor_id |
| uint32_t | hwcfg1 |
| uint32_t | hwcfg2 |
| uint32_t | hwcfg3 |
| uint32_t | hwcfg4 |
| uint32_t | core_lpm_configuration |
| uint32_t | global_powerDn |
| uint32_t | global_fifo_config |
| uint32_t | adp_control |
| uint32_t | reserved_0x64 [39] |
| uint32_t | host_periodic_tx_fifo_size |
| uint32_t | stuff [191] |
| uint32_t | reserved_0x800 [(0xe00-0x800)/sizeof(uint32_t)] |
| uint32_t | power |
Host registers | |
The registers beginning at this point are considered to be the "Host" registers. These are used for the "Host" half of the OTG (On-The-Go) protocol, which allows this hardware to act as either a USB host or a USB device. This is the only half we are concerned with in this driver and we do not declare the corresponding Device registers. | |
| uint32_t | host_configuration |
| uint32_t | host_frame_interval |
| uint32_t | host_frame_number |
| uint32_t | host_reserved_0x40c |
| uint32_t | host_fifo_status |
| uint32_t | host_channels_interrupt |
| uint32_t | host_channels_interrupt_mask |
| uint32_t | host_frame_list |
| uint32_t | host_reserved_0x420 [8] |
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union dwc_regs::dwc_host_port_ctrlstatus | host_port_ctrlstatus |
| uint32_t | host_reserved_0x444 [47] |
| struct dwc_regs::dwc_host_channel | host_channels [DWC_NUM_CHANNELS] |
| uint32_t | host_reserved_after_channels [(0x800-0x500-(DWC_NUM_CHANNELS *sizeof(struct dwc_host_channel)))/sizeof(uint32_t)] |
Layout of the registers of the DesignWare Hi-Speed USB 2.0 On-The-Go Controller. There is no official documentation for these; however, the register locations (and to some extent the meanings) can be found in other code, such as the Linux driver for this hardware that Synopsys contributed.
We do not explicitly define every bit in the registers because the majority are not used by our driver and would complicate this file. For example, we do not attempt to document any features that are specific to suspend, hibernation, the OTG protocol, or to the core acting in device mode rather than host mode.
The bits and fields we do use in our driver we have tried to completely document based on our understanding of what they do. We cannot guarantee that all the information is correct, as we do not have access to any official documentation.
| uint32_t dwc_regs::ahb_configuration |
0x008 : AHB Configuration Register.
This register configures some of the interactions the DWC has with the rest of the system.
| union dwc_core_interrupts dwc_regs::core_interrupt_mask |
0x018 : Core Interrupt Mask Register.
This register has the same format as the Core Interrupt Register and configures whether the corresponding interrupt is enabled (1) or disabled (0). Initial state after reset is all 0's.
| uint32_t dwc_regs::core_reset |
0x010 : Core Reset Register.
Software can use this register to cause the DWC to reset itself.
| uint32_t dwc_regs::host_channels_interrupt |
0x414 : Host All Channels Interrupt Register.
This register contains a bit for each host channel that indicates whether an interrupt has occurred on that host channel. You cannot clear the interrupts by writing to this register; use the channel-specific interrupt registers instead.
| uint32_t dwc_regs::host_channels_interrupt_mask |
0x418 : Host All Channels Interrupt Mask Register.
Same format as the Host All Channels Interrupt Register, but a 1 in this register indicates that the corresponding host channel interrupt is enabled. Software can change this register. Defaults to all 0's after a reset.
| uint32_t dwc_regs::host_periodic_tx_fifo_size |
0x100 : Host Periodic Transmit FIFO Size Register.
The low 16 bits of this register configure the offset of the Periodic Transmit FIFO, in 4-byte words, from the start of the memory reserved by the controller for dynamic FIFOs. The high 16 bits of this register configure its size, in 4-byte words.
This register should be set by software before using the controller; see the note in the documentation for the hwcfg3 register about configuring the dynamic FIFOs.
| uint32_t dwc_regs::hwcfg3 |
0x04c : Hardware Configuration 3 Register.
The high 16 bits of this read-only register contain the maximum total size, in words, of the dynamic FIFOs (Rx, Nonperiodic Tx, and Periodic Tx). Software must set up these three dynamic FIFOs in the rx_fifo_size, nonperiodic_tx_fifo_size, and host_periodic_tx_fifo_size registers such that their total size does not exceed this maximum total size and no FIFOs overlap.
Note: Software must explicitly configure the dynamic FIFOs even if the controller is operating in DMA mode, since the default values for the FIFO sizes and offsets may be invalid. For example, in Broadcom's instantiation of this controller for the BCM2835, only 4080 words are available for dynamic FIFOs, but the dynamic FIFO sizes are set to 4096, 32, and 0, which are invalid as they add up to more than 4080. IF YOU DO NOT DO THIS YOU WILL GET SILENT MEMORY CORRUPTION.
The low 16 bits of this register contain various flags that are not documented here as we don't use any in our driver.
| uint32_t dwc_regs::nonperiodic_tx_fifo_size |
0x028 : Non Periodic Transmit FIFO Size Register.
The low 16 bits of this register contain the offset of the Nonperiodic Transmit FIFO, in 4-byte words, from the start of the memory reserved by the controller for dynamic FIFOs. The high 16 bits of this register contain its size, in 4-byte words.
This register must be set by software before using the controller; see the note in the documentation for the hwcfg3 register about configuring the dynamic FIFOs.
| uint32_t dwc_regs::rx_fifo_size |
0x024 : Receive FIFO Size Register.
This register contains the size of the Receive FIFO, in 4-byte words.
This register must be set by software before using the controller; see the note in the documentation for the hwcfg3 register about configuring the dynamic FIFOs.
1.8.5
