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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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#include <usb_dwc_regs.h>
Data Fields | |
| uint32_t | val |
| struct { | |
| uint32_t connected: 1 | |
| uint32_t connected_changed: 1 | |
| uint32_t enabled: 1 | |
| uint32_t enabled_changed: 1 | |
| uint32_t overcurrent: 1 | |
| uint32_t overcurrent_changed: 1 | |
| uint32_t resume: 1 | |
| uint32_t suspended: 1 | |
| uint32_t reset: 1 | |
| uint32_t reserved: 1 | |
| uint32_t line_status: 2 | |
| uint32_t powered: 1 | |
| uint32_t test_control: 4 | |
| uint32_t speed: 2 | |
| uint32_t reserved2: 13 | |
| }; | |
0x440 : Host Port Control and Status Register.
This register provides the information needed to respond to status queries about the "host port", which is the port that is logically attached to the root hub.
When changing this register, software must read its value, then clear the enabled, connected_changed, enabled_changed, and overcurrent_changed members to avoid changing them, as those particular bits are cleared by writing 1.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::connected |
1: a device is connected to this port. 0: no device is connected to this port.
Changed by hardware only.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::connected_changed |
Set by hardware when connected bit changes. Software can write 1 to acknowledge and clear. The setting of this bit by hardware generates an interrupt that can be enabled by setting port_intr in the core_interrupt_mask register.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::enabled |
1: port is enabled. 0: port is disabled.
Note: the host port is enabled by default after it is reset.
Note: Writing 1 here appears to disable the port.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::enabled_changed |
Set by hardware when enabled bit changes. Software can write 1 to acknowledge and clear. The setting of this bit by hardware generates an interrupt that can be enabled by setting port_intr in the core_interrupt_mask register.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::line_status |
Current logic of data lines (10: logic of D+; 11: logic of D-).
Changed by hardware only.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::overcurrent |
1: overcurrent condition active on this port 0: no overcurrent condition active on this port
Changed by hardware only.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::overcurrent_changed |
Set by hardware when the overcurrent bit changes. The software can write 1 to acknowledge and clear. The setting of this bit by hardware generates the interrupt that can be enabled by setting port_intr in the core_interrupt_mask register.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::powered |
1: port is powered. 0: port is not powered.
Software can change this bit to power on (1) or power off (0) the port.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::reset |
Software can set this to start a reset on this port. Software must clear this after waiting 60 milliseconds for the reset is complete.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::resume |
Set by software to set resume signalling.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::speed |
Speed of attached device (if any). This should only be considered meaningful if the connected bit is set.
00: high speed; 01: full speed; 10: low speed
Changed by hardware only.
| uint32_t dwc_regs::dwc_host_port_ctrlstatus::suspended |
Set by software to suspend the port.
1.8.5
