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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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Embedded Xinu Operating System
An ongoing research project and educational operating system.
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#include <usb_dwc_regs.h>
Data Structures | |
| union | dwc_host_channel_characteristics |
| union | dwc_host_channel_interrupts |
| union | dwc_host_channel_split_control |
| union | dwc_host_channel_transfer |
Data Fields | |
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union dwc_regs::dwc_host_channel::dwc_host_channel_characteristics | characteristics |
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union dwc_regs::dwc_host_channel::dwc_host_channel_split_control | split_control |
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union dwc_regs::dwc_host_channel::dwc_host_channel_interrupts | interrupts |
| union dwc_host_channel_interrupts | interrupt_mask |
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union dwc_regs::dwc_host_channel::dwc_host_channel_transfer | transfer |
| uint32_t | dma_address |
| uint32_t | reserved_1 |
| uint32_t | reserved_2 |
0x500 : Array of host channels. Each host channel can be used to execute an independent USB transfer or transaction simultaneously. A USB transfer may consist of multiple transactions, or packets. To avoid having to re-program the channel, it may be useful to use one channel for all transactions of a transfer before allowing other transfers to be scheduled on it.
| uint32_t dwc_regs::dwc_host_channel::dma_address |
Channel DMA Address Register -
Word-aligned address at which the hardware will read or write data using Direct Memory Access. This must be programmed before beginning the transfer, unless the size of the data to send or receive is 0. The hardware will increment this address by the number of bytes successfully received or sent, which will correspond to the size decrease in transfer.size.
Note: DMA must be enabled in the AHB Configuration Register before this register can be used. Otherwise, the hardware is considered to be in Slave mode and must be controlled a different way, which we do not use in our driver and do not attempt to document.
BCM2835-specific note: Theoretically, addresses written to this register must be bus addresses, not ARM physical addresses. However, in our experience the behavior is the same when simply using ARM physical addresses.
| union dwc_host_channel_interrupts dwc_regs::dwc_host_channel::interrupt_mask |
Channel Interrupts Mask Register -
This has the same format as the Channel Interrupts Register, but software uses this to enable (1) or disable (0) the corresponding interrupt. Defaults to all 0's after a reset.
1.8.5
