usb_dwc_regs.h File Reference

#include <usb_util.h>

Go to the source code of this file.

Data Structures
struct	dwc_regs
union	dwc_regs::dwc_core_interrupts
union	dwc_regs::dwc_host_port_ctrlstatus
struct	dwc_regs::dwc_host_channel
union	dwc_regs::dwc_host_channel::dwc_host_channel_characteristics
union	dwc_regs::dwc_host_channel::dwc_host_channel_split_control
union	dwc_regs::dwc_host_channel::dwc_host_channel_interrupts
union	dwc_regs::dwc_host_channel::dwc_host_channel_transfer

Macros
#define	DWC_NUM_CHANNELS   8
#define	DWC_AHB_INTERRUPT_ENABLE   (1 << 0)
#define	BCM_DWC_AHB_AXI_WAIT   (1 << 4)
#define	DWC_AHB_DMA_ENABLE   (1 << 5)
#define	DWC_AHB_MASTER_IDLE   (1 << 31)
#define	DWC_SOFT_RESET   (1 << 0)

Detailed Description

Registers of the DesignWare Hi-Speed USB 2.0 On-The-Go Controller.

Macro Definition Documentation

#define BCM_DWC_AHB_AXI_WAIT   (1 << 4)

Bits [4:1] of the AHB Configuration register were redefined by Broadcom for the BCM2835; hence this flag is only valid on the BCM2835.

This bit is documented as:

1 = Wait for all outstanding AXI writes to complete before signalling (internally) that DMA is done. 0 = don't wait.

We set this bit because the Linux driver does, although we did not observe a difference in behavior.

#define DWC_AHB_DMA_ENABLE   (1 << 5)

Writing 1 to this bit in the AHB Configuration Register allows the USB controller to perform DMA (Direct Memory Access). Disabled by default.

#define DWC_AHB_INTERRUPT_ENABLE   (1 << 0)

Enable interrupts from the USB controller. Disabled by default.

#define DWC_AHB_MASTER_IDLE   (1 << 31)

TODO

#define DWC_NUM_CHANNELS   8

Number of DWC host channels, each of which can be used for an independent USB transfer. On the BCM2835 (Raspberry Pi), 8 are available. This is documented on page 201 of the BCM2835 ARM Peripherals document.

#define DWC_SOFT_RESET   (1 << 0)

Write 1 to this location in the Core Reset Register to start a soft reset. This bit will then be cleared by the hardware when the reset is complete.